The state of the art in the above-stated field includes U.S. Pat. No. 3,716,837 to Waddell, which shows broadcasting an untaggged interrupt signal from a peripheral system to a plurality of connected host processors. Any one of the connected host processors can respond to the broadcast untagged interrupt. This patent does not relate to a synchronous status between the various processors, rather it is directed primarily to broadcasting an untagged interrupt for handling by a first available host processor for servicing an attached peripheral data processing subsystem.
U.S. Pat. No. 3,670,307 to Arnold et al., shows a data storage subsystem which operates internally asynchronous to program execution in any of a plurality of attached host processors. Each of the input/output ports of the peripheral subsystem, as explained in column 7 of this patent, has a queue storing the received request from the various host processors. The subsystem then executes the received requests based upon its own program determined execution procedures independent of synchronization with the host processors. Host processor programs are not shown by Arnold et al. for establishing configuration data of the subsystem for such attached host processors, nor are the details of how the host processors may manage such asynchronous operations shown.
Byrns, U.S. Pat. No. 4,594,657, shows two asynchronously operating microprocessors. The microprocessors share status information about a shared memory using so-called semaphores. The semaphores, in turn, are used by program means for arbitrating access to the shared resource, a data storage unit or memory. This patent does not address management of such memory accesses nor the operation of such a memory asynchronously to the host processor program execution. It is to be appreciated that Byrns apparently operates the memory synchronously with respect to the two microprocessors, (equivalent of host processors) as is usual.
Neches et al., U.S. Pat. No. 4,412,285, also employ semaphores in a multiple processor environment. A single query or request is supplied from a peripheral system to all of the processors for determining readiness of a network. A well known "test and set" instruction or query is sent to all of the processors for determining the state of readiness of the network. While the broadcasting of a query to all units is shown, the management of asynchronous operations is not disclosed.
Schlaeppi, U.S. Pat. No. 3,480,914, shows "interaction units" connected to respective processors and to each other for operating indepdently from the host processors for avoiding interrupting host processor operation. The interaction processors appear to provide status information transfer as well as synchronizing operation of the multiple processor setup.
Frieder et al, U.S. Pat. No. 4,527,237, show a set of tightly coupled processors (tightly coupled implies synchronous operation) sharing a main memory. An I/O and supervisory processor are coupled to the main memory and to the various host processors for enabling the main memory to imply different data and control structures from the execution (host) and I/O processors. Status information is exchanged between the units. Because of the close operative association of the various units, it is believed that the operation is entirely synchronous; hence does not apply to managing an asynchronous set of peripheral devices.
Dirac, U.S. Pat. No. 3,405,394, teaches that a bit pattern can show access status of various units. Bit patterns are supplied by the various units and sensed by other units to determine when and how to access the diverse units within a multiple unit setup. Since access control is the main concern of this reference, it does not go into whether or not asynchronous operations are used. It does show that the transfer of bit patterns identify the status of a plurality of units within a data processing system.
Lorie et al., U.S. Pat. No. 4,445,197, show weakly synchronized multiple processors which coordinate their operations. An access priority system manages the system. This reference does not show the management of asynchronous management of a subsystem.
U.S. Pat. No. 4,099,235 shows a two-processor telephone switching node. Distribution of the processor loads between the two processors is based upon load measurements, i.e., it is a load balancing system. All the telephone operations are asynchronous with respect to each other. The patent appears to be directed solely to load management, and not to the management of the various status of the telephone calls going through the switching central as contemplated by the management techniques of this invention.
Based upon all of the above and the current trends in the data processing environments toward greater asynchronous operations between multiple units in a data processing environment, there is a clear need for the management and control of asynchronous operations, including the asynchronous reporting of configuration and peripheral device-state transitions or changes. All of the above should use program means for maximum efficiency and the transfer of status information to all concerned processing units.
The IBM Publication IBM System/360 and System/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information, supra, shows a connection between a control unit and a host processor with which the present invention may be advantageously employed. Of particular interest is the "attention signal" described on page 24. The attention signal is generated by the control unit when some asynchronous condition occurs in an I/O device. Attention is not associated with the initiaion, execution or termination of any I/O operation. Each I/O device shared between more than one channel path presents any attention status to all channel paths. Presentation of the attention signal by the peripheral control unit causes command chaining of the channel to the control unit to be suppressed. The attention signal can occur with other signals, including "device end". Device end is described on page 24 of the manual and results from either the completion of an I/O operation at the I/O device level or from changing the device operational state, such as from not ready to ready. Depending upon the environment in which the device end signal is supplied, it can have any one of several meanings to the connected channel; hence host processor. Device end is also presented whenever there is not a ready to ready transition of the device; such as, going from an unloaded to loaded condition of a magnetic tape drive, card equipment out of cards or stacker full, a printer out of paper, error conditions requiring human intervention or the status of the I/O device is changed from an enabled to disabled state.
A third signal described on page 27 of the referenced manual is "unit exception". Unit exception means that the identified I/O device detected an unusual peripheral condition, such as end of file. Generally a unit exception signal has only one meaning for any particular command or type of I/O device. Usually a "sense" operation by the host processor is not required as a response to the acceptance of a unit exception condition. Generally, the unit exception condition relates to some activity associated with an I/O operation or the condition is of immediate significance to the data processing environment for disk storage devices.
It has been a practice to combine the unit exception, device end and attention signals for indicating to the host processor that a "pack change interrupt" has occurred; that is, such as on the IBM 2314, 3330 disk drives, removably mounted disks were removed from such a disk drive. When the disks are removed from the drive, a pack change is defined as occurring. When any of the disk drives detect such a pack change, then the three signals, unit exception, attention and device end are simultaneously broadcast to the connected host processors. The host processors respond to such a broadcast set of signals to "sense" the volume then currently on the device to identify it.